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针对现有的忆阻仿真器工作频率低、范围小，且有源结构静态功耗高等劣势，设计了一种基于互补金属氧化物半导体(CMOS)的新型无源忆阻仿真器，采用130 nm工艺在Candence Virtuoso中实现了新型忆阻仿真器电路，仿真结果显示出显著的忆阻特性，且输入信号频率达300 MHz时依然有明显的捏滞曲线，PVT测试也显示出较强的稳定性。新型无源忆阻仿真器利用PN结和小电阻在信号输入时的压降使MOS管有效导通，消除了偏置电源，从而能够在浮地模式下良好运行，实现了零静态功耗。在面包板上，利用商用元件搭建了实物电路，测试结果显示出了忆阻器的捏滞回线，验证了电路可行性。运用新型无源忆阻器的比例逻辑结构(MRL)设计的逻辑门构建了上升沿D触发器，在此基础上设计了2 bits和4 bits的线性反馈移位寄存器(LFSR),并进一步设计了可自启动的计数器，仿真结果验证了电路功能的正确性，从而说明了新型无源忆阻仿真器在数字电路设计中的可行性。
Abstract：In addressing the limitations of existing memristor emulators, such as low operating frequency, narrow range, and high static power consumption in active structures, a novel passive memristor emulator based on complementary metal-oxide-semiconductor(CMOS) technology was developed. The new memristor emulator circuit was implemented using a 130 nm process in Cadence Virtuoso. Simulation results demonstrated significant memristive characteristic, with distinct pinched hysteresis curves observed even at an input signal frequency of 300 MHz. PVT(process, voltage, temperature) tests also indicated strong stability. The novel passive memristor emulator leverages the voltage drop across PN junctions and small resistors during signal input to effectively turn on MOS transistors, eliminating the need for bias power supplies and enabling operation in a floating ground mode, thereby achieving zero static power consumption. A prototype circuit was assembled on a breadboard using commercial components, and test results exhibited the pinched hysteresis loops characteristic of memristors, validating the circuit′s feasibility. Utilizing the memristive ratioed logic(MRL) structure of the novel passive memristor, logic gates were designed to construct a rising-edge D flip-flop. Based on this, 2-bit and 4-bit linear feedback shift registers(LFSRs) were designed, and a self-starting counter was further developed. Simulation results confirmed the correctness of the circuit functions, thereby demonstrating the feasibility of the novel passive memristor emulator in digital circuit design.
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基本信息:
DOI：
中图分类号:TN60
引用信息:
[1]杨思浩,代广珍.无源甚高频忆阻仿真器设计及计数器实现[J].山东师范大学学报(自然科学版),2025,40(03):271-282.
基金信息:
安徽省教育厅自然科学基金重点资助项目(批准号：2023AH050922); 安徽省车载显示集成系统工程研究中心与安徽省触摸显示材料与器件联合学科重点实验室联合开放资助项目(批准号：VDIS2023B03、VDIS2023B04、VDIS&TDMD2024B04)